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843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 1 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary g eneral d escription the ics843001bi is a fibre channel clock generator and a member of the hiperclocks tm family of high performance devices from ics. the ics843001bi uses either a 26.5625mhz or a 23.4375mhz crystal to synthesize 106.25mhz, 187.5mhz or 212.5mhz, using the freq_sel pin. the ics843001bi has excellent <1ps phase jitter performance, over the 637khz ? 10mhz integration range. the ics843001bi is packaged in a small 8-pin tssop and 16 vfqfn, making it ideal for use in systems with limited board space. f eatures ? one differential 3.3v lvpecl output ? crystal oscillator interface designed for 23.4375mhz or 26.5625mhz, 18pf parallel resonant crystal ? selectable 106.25mhz, 187.5mhz or 212.5mhz output frequency ? vco range: 560mhz - 680mhz ? rms phase jitter @ 106.255mhz, using a 26.5625mhz crystal (637khz - 10mhz): 0.60ps (typical) ? 3.3v operating supply ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs-compliant packages hiperclocks? ic s s t u p n i s e i c n e u q e r f t u p t u o y c n e u q e r f l a t s y r cl e s _ q e r f z h m 5 2 6 5 . 6 20 ) t l u a f e d ( z h m 5 2 . 6 0 1 z h m 5 2 6 5 . 6 21z h m 5 . 2 1 2 z h m 5 7 3 4 . 3 21z h m 5 . 7 8 1 f unction t able ics843001bi 8-lead tssop 4.40mm x 3.0mm x 0.925mm package body g package top view v cca v ee xtal_out xtal_in 1 2 3 4 v cc q nq freq_sel 8 7 6 5 osc phase detector vco 637.5mhz w/ 26.5625mhz ref. m = 24 (fixed) 1 0 6 3 b lock d iagram xtal_in xtal_out q nq freq_sel (pulldown) ics843001bi 16-lead vfqfn 3mm x 3mm x 0.95 package body k package top view v ee nc xtal_out xtal_in v cc q nq v ee v ee nc v cc freq_sel v cca nc nc nc 1 2 3 4 12 11 10 9 5 6 7 8 16 15 14 13 p in a ssignment the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specifications without notice.
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 2 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary t able 2. p in c haracteristics t able 1. p in d escriptions e m a ne p y tn o i t p i r c s e d v c c r e w o p. n i p y l p p u s r e w o p v a c c r e w o p. n i p y l p p u s g o l a n a v e e r e w o p. n i p y l p p u s e v i t a g e n , t u o _ l a t x n i _ l a t x t u p n i , t u p n i e h t s i n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i t u o _ l a t x l e s _ q e r ft u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . n i p t c e l e s y c n e u q e r f q , q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . s t u p t u o k c o l c l a i t n e r e f f i d c nd e s u n u. t c e n n o c o n : e t o n n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 3 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary t able 3a. p ower s upply dc c haracteristics , v cc = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s r e w o p 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v i a c c t n e r r u c y l p p u s g o l a n ai n i d e d u l c n i e e 8a m i e e t n e r r u c y l p p u s r e w o p 0 6a m t able 3c. lvpecl dc c haracteristics , v cc = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov c c 4 . 1 -v c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov c c 0 . 2 -v c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t c c . v 2 - t able 4. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 5 7 3 4 . 3 25 2 6 5 . 6 2z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 8 lead tssop 101.7c/w (0 mps) 16 lead vfqfn 51.5c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 3b. lvcmos/lvttl dc c haracteristics , v cc = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n il e s _ q e r fv c c v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n il e s _ q e r fv c c v , v 5 6 4 . 3 = n i v 0 =5 -a
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 4 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary t able 5. ac c haracteristics , v cc = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 1 = l e s _ q e r f7 6 . 6 8 16 6 . 6 2 2z h m 0 = l e s _ q e r f3 3 . 3 93 3 . 3 1 1z h m t ) ? ( t i j ; ) m o d n a r ( , r e t t i j e s a h p s m r 1 e t o n ) z h m 0 1 o t z h k 7 3 6 ( , z h m 5 . 2 1 20 6 . 0s p ) z h m 0 2 o t z h m 5 7 8 . 1 ( , z h m 5 . 7 8 1d b ts p ) z h m 0 1 o t z h k 7 3 6 ( , z h m 5 2 . 6 0 10 6 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 4s p c d oe l c y c y t u d t u p t u o 0 = l e s f0 5% 1 = l e s f0 5% . t o l p e s i o n e s a h p o t r e f e r e s a e l p : 1 e t o n
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 5 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary p arameter m easurement i nformation o utput d uty c ycle /p ulse w idth /p eriod o utput r ise /f all t ime 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v -1.3v 0.165v clock outputs 20% 80% 80% 20% t r t f v sw i n g pulse width t period t pw t period odc = q nq v ee v cc rms p hase j itter phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 6 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary a pplication i nformation figure 2. c rystal i npu t i nterface c rystal i nput i nterface the ics843001bi has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 2 below were determined using a 26.5625mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843001bi provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc and v cca should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc c1 33p x1 18pf parallel crystal c2 27p xtal_out xtal_in
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 7 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary f igure 3a. ics843001bi s chematic e xample l ayout g uideline figure 3a shows a schematic example of the ics843001bi. an example of lvepcl termination is shown in this sche- matic. additional lvpecl termination approaches are shown in the lvpecl termination application note. in this example, an 18pf parallel resonant crystal is used. the c1 = 27pf and c2 = 33pf are recommended for frequency accuracy. the c1 and c2 values may be slightly adjusted for optimizing fre- quency accuracy. f igure 3b. ics843001bi pc b oard l ayout e xample pc b oard l ayout e xample figure 3b shows an example of ics843001bi p.c. board layout. the crystal x1 footprint shown in this example allows installation of either surface mount hc49s or through-hole hc49 package. the footprints of other components in this example are listed in the table 6. there should be at least one decoupling capacitor per power pin. the decoupling ca- pacitors should be located as close as possible to the power pins. the layout assumes that the board has clean analog power ground plane. t able 6. f ootprint t able e c n e r e f e re z i s 2 c , 1 c2 0 4 0 3 c5 0 8 0 5 c , 4 c3 0 6 0 2 r3 0 6 0 t n e n o p m o c s t s i l , 6 e l b a t : e t o n . e l p m a x e t u o y a l s i h t n i n w o h s s e z i s vcca c1 27pf nq c4 0.01u q r5 133 r1 1k zo = 50 ohm vcc r6 82.5 18pf c5 0.1u c3 10uf + - u1 ics843001 1 2 3 4 8 7 6 5 vcca vee xtal _o u t xtal _i n vcc q0 nq0 freq_sel vcc r3 133 r4 82.5 vcc zo = 50 ohm x1 26.5625mhz r2 10 vcc c2 33pf
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 8 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843001bi. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843001bi is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 60ma = 207.9mw ? power (outputs) max = 30mw/loaded output pair total power _max (3.465v, with all outputs switching) = 207.9mw + 30mw = 237.9mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5c/w per table 7a below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.238w * 90.5c/w = 106.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 7a. t hermal r esistance ja for 8- pin tssop, f orced c onvection ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w t able 7b. ja vs . a ir f low t able for 16 l ead vfqfn ja at 0 air flow (linear feet per minute) 0 multi-layer pcb, jedec standard test boards 51. 5c/w
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 9 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 4. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc _max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc _max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 4. lvpecl d river c ircuit and t ermination q1 v out v cc rl 50 v cc - 2v
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 10 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary r eliability i nformation t ransistor c ount the transistor count for ics843001bi is: 2069 t able 8a. ja vs . a ir f low t able for 8 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w t able 8b. ja vs . a ir f low t able for 16 l ead vfqfn ja at 0 air flow (linear feet per minute) 0 multi-layer pcb, jedec standard test boards 51. 5c/w
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 11 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary p ackage o utline - g s uffix 8 l ead tssop t able 9a. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 20 1 . 3 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 12 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary p ackage o utline - k s uffix for 16 l ead vfqfn t able 9b. p ackage d imensions reference document: jedec publication 95, mo-220 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y sm u m i n i mm u m i x a m n 6 1 a 0 8 . 00 . 1 1 a 05 0 . 0 3 a e c n e r e f e r 5 2 . 0 b 8 1 . 00 3 . 0 e c i s a b 0 5 . 0 n d 4 n e 4 d 0 . 3 2 d 5 2 . 05 2 . 1 e 0 . 3 2 e 5 2 . 05 2 . 1 l 0 3 . 00 5 . 0
843001bki www.icst.com/products/hiperclocks.html rev. a october 6, 2005 13 integrated circuit systems, inc. ics843001bi f emto c locks ? c rystal - to - 3.3v lvpecl c lock g enerator preliminary t able 10. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not aut horize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademarks, hiperclocks and femtoclocks are trademarks of integrated circuit systems, inc. or its subsidiari es in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t i g b 1 0 0 3 4 8 s c id b tp o s s t d a e l 8e b u tc 5 8 o t c 0 4 - t i g b 1 0 0 3 4 8 s c id b tp o s s t d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i g b 1 0 0 3 4 8 s c id b tp o s s t " e e r f - d a e l " d a e l 8e b u tc 5 8 o t c 0 4 - t f l i g b 1 0 0 3 4 8 s c id b tp o s s t " e e r f - d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - i k b 1 0 0 3 4 8 s c id b tn f q f v d a e l 6 1e b u tc 5 8 o t c 0 4 - t i k b 1 0 0 3 4 8 s c id b tn f q f v d a e l 6 1l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l i k b 1 0 0 3 4 8 s c id b tn f q f v " e e r f - d a e l " d a e l 6 1e b u tc 5 8 o t c 0 4 - t f l i k b 1 0 0 3 4 8 s c id b tn f q f v " e e r f - d a e l " d a e l 6 1l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n

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